EPROMs are memory devices typically programmed by an end user as data or instructions used by a microprocessor to perform a desired function. Presently, most EPROMs are asynchronous devices. However, synchronous EPROM are now available, such as burst EPROMs of the type disclosed in co-pending application Ser. No. 758,141 filed Dec. 28, 1989, now U.S. Pat. No. 5,159,672. To ensure proper operation, the access time of synchronous EPROMs must be compatible with the clock speed and read cycle times of the microprocessor. In this connection, one way to ensure compatibility between a microprocessor and such an EPROM is to provide the EPROM with a number of wait states (i.e., microprocessor clock cycles, typically 0, 1, 2 or 3) between an IDLE state and an initial DOUT (data out) state. For this reason, although two EPROMs may be functionally identical, if used in conjunction with microprocessors having different clock speeds, the two EPROMs must be manufactured so that one incorporates the number of wait states needed for proper operation with one microprocessor, and the other incorporates the number of wait states needed for proper operation with the second microprocessor. For example, the different EPROMs could be manufactured using different metal masks which would produce different numbers of wait states. However, this approach results in a decrease in manufacturing flexibility since to meet customer delivery requirements, EPROMs must be available from an existing inventory of the manufacturer, rather than custom made. Of course, maintaining an inventory of EPROMs which are identical except for the number of wait states increases their cost.
Alternatively, the EPROMs could be manufactured so that the end user could set the number of wait states by, for example, a pin strapping option. However, this approach would increase the number of pinouts, which again results in increased costs.
Another approach commonly used is to require the microprocessor to insert wait states when accessing an attached EPROM as a function of the clock frequency and speed of the EPROM. However, this approach requires that the interface between the microprocessor and EPROM include a mechanism for informing the microprocessor of the speed of the EPROM such as a handshake signal. However, this approach increases the number of pinouts, increases design complexity and may result in a decrease in performance during EPROM accesses.